The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 1989
Filed:
Dec. 11, 1987
Fumihiko Kuroda, Kashiwa, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
The invention discloses a method including the following processes (a) through (c) for forming impurity regions in a semiconductor device (a) a process that forms at least one second conductive type impurity-doped region by doping second conductive type impurity selectively to a predetermined region of a first conductive type semiconductor layer constituting a semiconductor substrate, (b) a process that forms on the surface of the semiconductor substrate a diffusion mask having a first opening for exposing at least one of the second conductive type impurity regions and having a second opening for exposing a part adjacent to at least one of the second conductive type impurity regions, (c) a process that forms the second conductive type impurity region and a low concentration second conductive type impurity region being in contact with the former by out-diffusing through the first opening the second conductive type impurity of the second conductive type impurity region and re-doping the out-diffused impurity through the second opening to the first conductive type semiconductor layer. According to the method, an impurity region having a high breakdown voltage is formed by simple processes to have a smooth lateral concentration profile by means of vaporization and re-diffusion of the impurity previously doped to a semiconductor layer.