Speed-up circuit for transistor logic output device

Abstract

A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off. Then, when base current is supplied to the current-sink transistor to turn it on, the discharge transistor is held off for an amount of time during which all of the base current is provided to the current-sink transistor, causing it to be quickly switched on. Then the discharge transistor is turned on, permitting it to discharge the parasitic capacitance of the current-sink transistor at the next input signal transition.