Selectively recursive pipelined parallel vector logical operation system

Abstract

A vector logical operation apparatus includes first and second registers respectively for sequentially receiving first and second sets of vector elements which first and second sets of vector elements are supplied in pairs on the same sequential clock periods; third register; a plurality of first gates connected to the first and third registers each for performing a first bitwise logical operation on bit signals partly provided from the first register and the third register; a plurality of second gates connected to the second register and the first gates in a bitwise manner each for performing a second bitwise logical operation on bit signals provided from the second register and the first gates; a feed back circuit connected to the plurality of second gates for supplying the outputs of the second gates to the third register; and control circuit connected to the third register for ordering the third register to receive an applied initial data signal on or before supply of a pair of the first vector element of the first set and second set and to repeatedly receive the outputs of the second gates provided by the feed back circuit on sequential clock periods each clock period being one clock period later after receipt a pair of vector elements by the first and second registers; wherein the first and second gates are operable fast enough so that the outputs of the second gates at the end of each clock period fully responds to vector elements held by the first to third registers at the beginning of each clock period.