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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4792842 B1

PDFFull Text
Date of Patent:
Dec. 20, 1988

Filed:

Nov. 24, 1987

Semiconductor device with wiring layer using bias sputtering

Applicant:
Inventors:

Yoshio Honma, Nishitama, JP;

Sukeyoshi Tsunekawa, Tokorozawa, JP;

Natsuki Yokoyama, Mitaka, JP;

Hiroshi Morisaki, Hachioji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry & Wands

Primary Examiner:

Andrew J James

Assistant Examiner:

William A Mintel

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 71 ; 357 65 ; 357 68 ;
Abstract

Disclosed is a semiconductor device and method for manufacturing the same, which is provided with a first wiring layer whose thickness within a contact hole is great in a lower portion of the contact hole and is small in an upper portion thereof. Since the first wiring layer at the lower portion of the contact hole is sufficiently thick, reaction between a second wiring layer formed on the first wiring layer and a substrate is effectively prevented. The first wiring layer is formed by bias sputtering in which a bias voltage is applied to the substrate.

Find Patent Forward Citations

Honma, Yoshio. (1988). Semiconductor device with wiring layer using bias sputtering (U.S. Patent No. 4792842). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4792842

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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