The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 1988
Filed:
Jan. 28, 1988
James S Butcher, Phoenix, AZ (US);
Siemens Transmission Systems, Inc., Phoenix, AZ (US);
Abstract
A center frequency high resolution digital phase-lock loop circuit (CF HRDPLL) is described with an input clock reference frequency which is equal to the output phase-locked frequency. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays. A 360 degree phase detector initializes the shift register to provide no delay when the output is delayed by almost one period of the input clock and a phase retard correction occurs. An advance correction from a no delay condition causes a fast shift to occur to locate one period of delay while the output is held at no delay. The output is then switched to slightly less than one period of phase delay to allow further phase advance corrections to occur. Gate delay variations due to process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.