Vector data logical usage conflict detection

Abstract

A system for detecting and resolving logical usage conflicts is described for use in a scientific data processing system. A plurality of pipelined overlapping macro instructions request access to the system memory. Often the information required by a subsequent instruction is not available until an earlier overlapped instruction has been completed thereby creating a conflict. This conflict is sensed by the subsequent instruction and memory access is delayed a number of memory cycles until the correct information is available at which time the subsequent instruction is allowed to proceed. This allows a scientific vector support processor having a high degree of asynchronism to be able to produce results as if no overlap existed to provide program execution results as if each instruction were executed serially to completion in the proper program order. There are three categories of data logical usage conflicts. First, a Write/Read conflicts occurs where there is an attempt to read a result vector element of an earlier instruction before the result vector is written. Next, a Read/Write conflict occurs when there is an attempt to overwrite a source vector element of an earlier instruction before it has been read. Finally, a Write/Write conflict occurs where there is an attempt to overwrite a result vector element of an earlier instruction before it is written.