The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 1988

Filed:

Jun. 25, 1987
Applicant:
Inventor:

Nader Vasseghi, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307310 ; 307456 ; 307466 ;
Abstract

An interface circuit (110) for interfacing between an 'OR-tied' connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circuit (42), and a sensing circuit (26). The first bandgap generator (40) generates a first reference voltage (VB1) which has a positive temperature coefficient. The second bandgap generator (42) generates a second reference voltage (VB2) which has a negative temperature coefficient. A resultant base drive current (I.sub.x) is supplied to the base of a phase splitter transistor (Q2) in the output buffer (36). The resultant current (I.sub.x) is controlled by the first and second bandgap generators (40, 42), the current being higher at low temperatures and being smaller at high temperatures.


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