The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 1988

Filed:

May. 16, 1986
Applicant:
Inventor:

Kiichiro Tamaru, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

A multi-level priority interrupt system is used for controlling the access of input/output control devices to a host computer which is connected to the devices and controls their operation. The input/output control devices each of which is contained on a different LSI chip, output different levels of interrupt requests to the host computer. During operation, each input/output control device outputs an interrupt signal of a frequency determined by a level of an interrupt to be sent to the host computer. The interrupt signal is supplied from one external terminal of the input/output control device. Upon receipt of the interrupt signals, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine.


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