The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 1988
Filed:
Jul. 16, 1987
Applicant:
Inventors:
Kouji Tanagawa, Tokyo, JP;
Tomoaki Yoshida, Minatoku, JP;
Assignee:
Oki Electric Industry Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
3072 / ; 3072 / ; 307362 ; 307443 ; 307448 ;
Abstract
A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.