The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 1988
Filed:
Jun. 26, 1986
Chu C Nei, San Jose, CA (US);
Dan R Hafeman, Sunnyvale, CA (US);
William Fazakerly, Saratoga, CA (US);
Ikos Systems, Inc., Sunnyvale, CA (US);
Abstract
Races and hazards in simulated logic designs are more easily detected if the logic simualtor is able to warn the designer of the presence of glitches. A glitch wall occur at the output of a logic device if an input condition causes the output to begin to change but the input condition is not present for sufficient time to allow the output to reach its stable state. The logic evaluator is the component of the logic simulator which is responsible for determining the output of a simulated device when the inputs to that device are known. The glitch detecting logic evaluator according to the present invention provides glitch detection by forcing the simulated device output to the undefined state when the device inputs change in a manner which does not allow the change to propagate to the output before a subsequent change occurs. The algorithms are designed for implementation in hardware for high performance logic simulation.