The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 1988

Filed:

May. 24, 1984
Applicant:
Inventor:

Eiji Masuda, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307290 ; 307279 ; 307268 ; 307601 ; 307602 ;
Abstract

An input signal level detecting circuit includes a first inverter group circuit having first and second inverters connected in series, and a second inverter group circuit having third and fourth inverters connected in series. The input terminals of the first and third inverters are supplied with a signal having first and second levels to be detected. The output terminals of the second and fourth inverters are connected to set and reset terminals of the flip-flop circuit. When the mean level of the first and second levels is V.sub.TM and the threshold voltages of the first to fourth inverters are V.sub.T1 to V.sub.T4, respectively, the relations V.sub.T1 >V.sub.TM ; V.sub.T2 <V.sub.TM ; V.sub.T3 <V.sub.TM and V.sub.T4 >T.sub.TM are satisfied.


Find Patent Forward Citations

Masuda, Eiji. (1988). Input signal level detecting circuit (U.S. Patent No. 4786824). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4786824

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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