The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 1988
Filed:
Apr. 17, 1987
Masato Abe, Sagamihara, JP;
Fumitaka Asami, Kunitachi, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.