Static cmos programmable logic array

Abstract

A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.