The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1988
Filed:
Nov. 10, 1986
Applicant:
Inventor:
Hiroshi Suzuki, Kamakura, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371-3 ;
Abstract
A forced error generating circuit for a data processing unit comprises a forced error register for generating a designation signal to forcibly cause an error for a structural element in the data processing unit and a signal generating means which receives a signal for starting a period for causing the error by a forced error generating instruction and generates a forced error generating signal corresponding to said designation signal during said period.
Suzuki, Hiroshi. (1988). Forced error generating circuit for a data processing unit (U.S. Patent No. 4779271). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4779271
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile