The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 1988
Filed:
Jul. 29, 1986
William E Moss, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ('NMOS') transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.