High speed successive approximation register in analog-to-digital

Abstract

In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A '0' propagates through the shift register at the DAC conversion rate. Beginning with the most significant bit (MSB), each successive digital approximation number applied to the DAC consists of a '1' gated to the DAC by the shift register bit presently containing the propagating '0'. After the present digital approximation number has been compared (by a comparator) to the analog input current, the resulting comparator data is latched into the data latch as the '0' shifts to the next bit. When the procedure has been completed for all N bits, the N bit word stored in the N data latches accurately represents the analog input current.