The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 1988

Filed:

Sep. 30, 1987
Applicant:
Inventors:

Atsushi Hayami, Yamato, JP;

Tsuyoshi Ono, Yamato, JP;

Kazuo Hikawa, Mitaka, JP;

Takeshi Shimizu, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
331 25 ; 329122 ; 358188 ; 455266 ;
Abstract

This invention relates to a digital audio tape recorder using a rotary magnetic head. On the tape which has been recorded using R-DAT, signals forming to the industry standards are recorded at a standard tape speed. The tape is caused to run at a speed faster than the standard tape speed and the recording signal is subjected to high speed reproducing while maintaining the rotational frequency of the head at a rotational speed at the time of recording. For realizing this, a bit clock signal generator for use in a digital signal demodulator is provided, which comprises means for generating a detection window pulse having a predetermined pulse width shorter than a period of a bit clock signal from either of time points of rise and fall of the waveform of a signal to be demodulated, or from both the time points thereof, said signal to be demodulated being a digital signal modulated in accordance with a modulation system such as a system constituted with a periodical signal intermittently including a phase information of the bit clock signal to deliver the detection window pulse to a phase locked loop including a phase comparison circuit and a voltage controlled oscillator as a comparison wave, thus allowing the voltage controlled oscillator in the phase locked loop to generate a bit clock signal, characterized by the provision of means for changing the pulse width of the detection window pulse in correspondence with changes in a bit rate of the demodulated signal.


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