The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 1988
Filed:
Apr. 09, 1985
David G Fox, Bedford, MA (US);
John R Mann, III, Boston, MA (US);
AOI Systems, Inc., , US;
Abstract
An apparatus for automatic printed wiring board (PWB) defect detection comprises an array of optical sensors for optically inspecting a printed wire circuit. The array forms a binary image pattern of the PWB which is tested for compliance with logical rules of correctly printed PWB's regarding unterminated conductors; a set of minimum and maximum specified line widths; line spacing width; presence of insulators on conductors and vice versa; presence of pinholes, flecks of copper, and Vees and neck-downs. A method employs an inner enable pattern of pixel bits formed to determine if a feature being viewed is possibly on a conductor line or insulator space. A set of same-state patterns is formed around the center of the matrix with each pattern being progressively larger. The state of opposite pixel points on the same-state patterns is progressively examined to determine the first inner pattern in which opposite pixel points are ot in the same state. Measurement and verification patterns are selected based upon which same-state pattern meets the above test. The measurement pattern is used to determine if the feature is centered in the matrix and the dimensions of the measurement pattern are checked against stored dimensions of acceptable size. The verification pattern is used to ascertain feature characteristics by counting the number of opposite verification pattern pixels, both on conductor, both on insulator and in opposite states and the number of transitions.