Digital scrambling without error multiplication

Abstract

The present invention describes a circuit which allows a data stream to be scrambled by continuously running uninterrupted Pseudo Random sequence without multiplying errors. This is accomplished by allowing a register in the Pseudo Random scrambling receiver to acquire synchronization with a register in the Pseudo Random scrambling transmitter such that the two registers run independently through the same maximal length Pseudo Random sequence without further need for communication with each other. Bit errors occurring between the transmitter and receiver do not cause the scrambling registers at the two ends to become out of synchronization and they remain in synchronism unless a timing slip occurs to cause the transmitter and receiver to lose synchronization. While the present invention is primarily directed toward providing a circuit for performing maximal length Pseudo Random scrambling without error multiplication, the invention is particularly advantageous in reducing the error rate under conditions in which a majority of the error bursts are comprised of one or a small number of error bits such as occurs in transmission loops where impulse noise is a problem.