Digital video delay by sample interpolation

Abstract

A video display apparatus convergence and correction arrangement includes a digital signal delay circuit which uses a sample interpolation technique to provide apparent signal delays corresponding to fractional parts of whole sample periods. Adjacent digital samples are combined using fractional coefficients that sum to unity. The selection of the fractional coefficients determines the size of the smallest delay increment. The number of whole sample delay periods as well as the initial fractional coefficients for a given horizontal scan line are provided by information that is stored in a memory device during assembly or alignment of the video display apparatus.