Concurrent fault simulation for logic designs

Abstract

A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the 'fault operation' for each fault condition for each gate, and comparing the corresponding results against the 'good machine' operation, and storing the fault operation if different from the good operation. By repeating the process on an event-driven basis from gate to subsequently affected gates throughout the design, a file of all fault effects can be developed from which an input test set for the logic design can be developed based on considerations of the required percentage of all possible faults to be detected and the time that can be allowed for testing of each chip. Special hardware is provided for identifying and eliminating hyperactive or oscillating faults to maintain processing efficiency.