Circuit arrangement comprising a matrix-shaped memory arrangement for

Abstract

A circuit arrangement comprises a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions and contains three-transistor cells having overlapping write/read cycles as storage elements. A row selector is clocked controlled by the input clock of the incoming image signals and is continuously steppable and resettable at any time. The row selector comprises, respectively, two phase offset signal outputs per selection step which respectively drive a write word line and a read word line and which are provided per row of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of the column. A storage amplifier which is disconnectible from the read bit line is provided per column and has an input connected to the read bit line of the assigned column and an output connected to the bit write line of the following column and serves as a data output. A reset input is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time to be set between the undelayed data output and a first, delayed data output. A plurality of such memory-shaped memory arrangements is provided in accordance with the word width of the image data the row selector being provided in common for such plurality, whereby a respective memory block accepts one bit of the image data word and offers the same as the respective corresponding bit of a plurality of differently time delayed output data words. An arithmetic unit combines the data outputs, by adding or, respectively, subtracting, in an arrangement of cascaded logic elements in order to achieve the required filter function.