Circuit for providing high sampling rate resolution using slow sampling

Abstract

The disclosure relates to a circuit using a relatively inexpensive low sampling rate resolution A/D converter for sampling repetitive signals which provides resolution far superior to that obtained normally from the converter being used. This is accomplished by providing a programmable variable delay which delays the system clock signal with respect to the trigger signal and controls the A/D converter with the delayed clock signal. The A/D converter receives input signal initiated by a flip flop responsive to a system start signal and the clock signal. The delay is varied for successive sampling of the repetitive signal received from the system under test so that sampling takes place at numerous points along the test signal. The converted signals are stored under joint control of the delayed clock signals and the output of the initiating signal from the flip flop. A gated clock circuit is used where an externally generated trigger is being used.