The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 1988

Filed:

Oct. 30, 1987
Applicant:
Inventors:

William D Hinsberg, III, Fremont, CA (US);

Webster E Howard, Yorktown Heights, NY (US);

Carlton G Willson, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 41 ; 437228 ; 437229 ; 437909 ; 437181 ; 148D / ; 357 237 ; 430312 ;
Abstract

A process for making a self-aligned thin film transistor, said process comprising the steps of: (1) providing a gate which comprises a glass substrate, a transparent electrode on top thereof, and a metal electrode on top of said transparent electrode, (2) forming a stack by depositing over said gate a triple layer structure consisting of gate dielectric material, active material and a top passivating dielectric, (3) coating the top of said triple layer with a dual-tone photoresist, (4) exposing said photoresist from the top through a mask having transparent areas, opaque areas and areas transparent to selective wavelengths, using broad band UV light, (5) developing the photoresist by treatment with a solvent, (6) etching the stack with a liquid etchant through to the glass substrate, (7) exposing the photoresist from the bottom through the glass substrate using near UV light, (8) developing the photoresist with a solvent, and (9) etching off the top passivating layer of the stack.


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