High-performance multiple port memory

Abstract

Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle. The pointer directs memory accessing to prevent conflicts. Conflicts are always avoided because one bank in each of the r groups is directed to supply data in response to a read address and the w remaining banks are available for writing data in response to the w write addresses redundantly so that each of the groups of memory banks will have valid data in at least one of its w+1 memory banks for a given address.