Slip control in a plesiochronous buffer circuit to reduce distortion of

Abstract

For a buffer memory used in a plesiochronous buffer circuit for reception of a PCM signal at station clocks and transmission thereof at satellite clocks, first and second partial write control arrangements control writing of first and second parts of each frame of each multiframe of the PCM signal, respectively, in accordance with the station clocks. First and second partial read controlling arrangements control reading of the buffer memory for the first and the second parts, respectively, in accordance with the satellite clocks. The buffer circuit is likewise operable when such a PCM signal is received at the satellite clocks. In this manner, the buffer circuit individually deals with the first and the second parts. Preferably, first and second comparing circuits produce first and second slip control signals, respectively, when the reading becomes near relative to the writing than one multiframe and one frame to slip the reading relative to the writing.