Cmos process flow with small gate geometry ldo n-channel transistors

Abstract

A process for forming lightly doped drains in a CMOS circuit utilizing two photoresist masks is disclosed. After gates for N-channel and P-channel transistors have been formed, an N-implant is effected. A first photoresist mask is used as a source/drain implant is made for the P-channel transistor. Sidewall spacers are formed for the gates of both transistors. A second photoresist mask is used as a source/drain implant is made for the N-channel transistor. The resulting CMOS circuit has an N-channel transistor with a lightly doped drain and a P-channel transistor without a lightly doped drain.