High density non-charge-sensing dram cell

Abstract

A non-charge-sensing high density dynamic random access memory (DRAM) cell using a trench capacitor as a vertical FET and two active field effect transistors (FETs). A particular bit line is shared by the cells on either side of it; the bit line on one side of a particular cell being used to write to the cell while the bit line on the other side of the cell is used to read from the cell. This dual use of bit lines, plus the use of a vertical FET transistor along one side of a trench capacitor, plus the avoidance for the need of a relatively large storage capacitor since the cell is not read by 'dumping' or releasing its charge onto the bit line all aid in making this cell compact and suitable for high density memories. Since the substrate serves as the second source/drain region of the vertical FET, a separate line for this region is eliminated, also contributing substantially to a smaller cell size.