The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 1988

Filed:

Dec. 17, 1985
Applicant:
Inventors:

Robin W Cheung, Cupertino, CA (US);

Hugo W Chan, Fremont, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 63 ; 437982 ; 437984 ;
Abstract

An integrated circuit fabrication technique for constructing field isolation structure components and subposing electrical barrier isolation region components in a substrate is disclosed. A nitride-less mask is used to pattern a major surface of the substrate with apertures where the isolation barrier components are to be implanted. Following the formation of the isolation components, a thick oxide is formed on the substrate, masked, and etched to form field oxide structures on the major surface of the substrate. Bird beaks, bird crests, crystalline dislocations and white ribbon problems associated with nitride masking processes are virtually eliminated.


Find Patent Forward Citations

Cheung, Robin. (1988). Nitride-less process for vlsi circuit device isolation (U.S. Patent No. 4762805). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4762805

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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