Tag control circuit for increasing throughput of main storage access

Abstract

A tag control circuit is provided in a memory access control apparatus of a digital computer system which also includes a central processor having a buffer storage. The tag control circuit includes a tag information store and update circuit and a necessity operation circuit for determining whether invalidation of the tag information and whether transmission of an invalidation information to the central processor are necessary. The tag control circuit also includes a first storage for storing a plurality of access requests of the invalidation operation determined by the necessity operation circuit, a second storage for storing a plurality of invalidation execute information determined by the necessity operation circuit, and a selection circuit receiving a new access request and an access request stored in the first storage and outputting one access request. The tag control circuit may further include a third circuit storage for storing only store access requests before supplying them to the necessity operation circuit, the third storage having an output connected to the request receiving and outputting circuit. The access selection circuit may output one request at a time the following priority order: a new read access request before an access request stored in the first storage and either before a store access request stored in the third storage.