The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 1988
Filed:
Nov. 05, 1987
Harold L Davis, The Colony, TX (US);
Robert J Proebsting, Argyle, TX (US);
SGS-Thomson Microelectronics, Inc., Carrollton, TX (US);
Abstract
A planar array of memory cells is controlled by row lines (word lines) for each row of cells and column lines each serving adjacent columns of cells as well as bit lines interlaced with the column lines so that all memory cells are connected between a column line and a bit line. The least significant bit of the column address provided by the column decoder selects between two sets of bit lines that are interlaced in altercation determining on which side of the column line the selected column will be found. In consequence, the selection of the column line and a set of bit lines selects only one column of cells. Enough columns of the array are selected at one time to address an entire logical field of data bits and also a set of parity bits related to the logical field of data bits. Each row of cells contain L (=16) logical fields, the individual data and parity cells of which are separated from each other by one cell of each of the other logical fields, so that a localized malfunction of the integrated circuit will not produce an error in more than one bit of any one logical field.