Signal sorting element with internal signal address value sorting

Abstract

A circuit element incorporating a logic circuit and a constant address number signal source which serves distinguish one circuit element from others that are otherwise similar, has two inputs (A) and (B), a low output (L) and a high output (H). This element utilizes the address portions of respective digital signal bytes provided respectively to its two outputs, to determine whether the A input will go to the low output and the B input to the high output or vice versa. The element includes, in addition to the address source, a detector for null address portions at each output and a switch responsive to the null detector for substituting the internally stored address number for the input address when a null address portion is detected. The logic circuit also includes an equality detector, for comparing the outputs of the respective switches, which cooperates with the null detector for the A input and an AND-gate to produce a control signal when the switch outputs are equal and the null detector for the A input detects a null address portion. Another comparator produces a control signal when the output of the switch controlled by the A input is greater than the output of the other switch. An OR-gate permit a control signal from either of the sources just described to be operative for connecting the A input to the high input and the B input to the low output.