Decoder circuit for a static random access memory

Abstract

An elementary decoder circuit for a monolithically integrated static random access memory is constructed by means of gallium arsenide field effect transistors and formed by a NOR-gate whose n inputs receive the n coded addressing signals a.sub.1, a.sub.2, . . . , a.sub.n of the memory, or their complements, and whose output supplied a signal which is applied to the upper transistor of a push-pull stage as well as a complementary signal, obttained via an inverter transistor, which is applied to the lower transistor of the push-pull stage. The junction point of the two transistors of the push-pull stage supplies the word line signal of the memory, and the two transistors of the push-pull stage are of the enhancement type, like the transistors of the NOR-gate, the output signal of the NOR-gate being applied to the input of the inverter transistor via a level shifting diode so that the biasing of the transistors of the push-pull stage results in an extremenly fast data transfer from the output of the NOR-gate to the word line.