The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 1988

Filed:

Jun. 29, 1987
Applicant:
Inventor:

Seung-Mo Seo, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307452 ; 307443 ; 307582 ; 307242 ;
Abstract

A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.


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