The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 1988

Filed:

Feb. 11, 1986
Applicant:
Inventors:

Kouji Tanaka, Kanagawa, JP;

Yoshihiro Ikeda, Kanagawa, JP;

Ryuzo Sugiura, Tokyo, JP;

Junzo Kikuchi, Kanagawa, JP;

Hikaru Sano, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04Q / ; H03K / ;
U.S. Cl.
CPC ...
379165 ; 307359 ; 375-7 ; 328150 ;
Abstract

There is disclosed a data transmitting and receiving circuit extremely advantageous when applied to a key telephone system. The data transmitting circuit comprises a voltage dividing circuit for dividing a power supply voltage to apply the divided voltage to one end of a primary winding of a transformer, and a driver circuit comprising a pair of transistors connected in series between the power supply and a common potential terminal, the node of the transistors being connected to the other end of the primary winding of the transformer. When data signal is transmitted, the data transmitting circuit is operative to complementarily turn and off the pair of transistors in accordance with the data signal. In contrast, when data is not transmitted, the data transmitting circuit is operative to cut off both the transistors. Thus, the data transmitting circuit can eliminate the possibility that a DC voltage on which a data signal to be transmitted is superimposed undesirably changes. Further, the data receiving circuit comprises a voltage divider common to the above-mentioned voltage dividing circuit, a comparator having a comparison input connected to the other end of the secondary winding of the transformer, and a reference voltage supply circuit for selecting either of two reference voltages depending upon a binary output level of the comparator to deliver the selected one to the reference input of the comparator. Thus, the data receiving circuit can provide a stable and steady receiving condition when a data signal superimposed on a DC voltage is received to change the data signal into a binary received signal.


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