The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 1988
Filed:
Dec. 28, 1984
Akira Yamamoto, Yokohama, JP;
Toru Nishigaki, Sagamihara, JP;
Miho Nonomura, Yokohama, JP;
Takashi Doi, Hadano, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An input/output control system has a control unit including a first controller connected between a channel and a data buffer for controlling the transfer of data therebetween and a second controller connected between the data buffer and a plurality of input/output devices for controlling the transfer of data therebetween. A start action of the input/output device is effected in an off-line mode from the control unit. The amount of data stored in the data buffer is checked each time the transfer of data occurs between the channel and the data buffer. In the case of a read processing, when the amount of data stored in the data buffer becomes less than a first predetermined value, data is transferred for preload from the input/output devices to the data buffer. In the case of a write processing, when the amount of data stored in the data buffer exceeds a second predetermined value, data is transferred for after-write from the data buffer to the input/output devices. Each of the first and second predetermined values is determined depending on the amount of input/output devices which are in an active state at that time. When each of the active input/output devices is allocated with m (.gtoreq.2) unit fields of the data buffer each of which has a capacity of K/(mn) where K is the whole capacity of the data buffer and n is the number of the active input/output devices, the first and second predetermined values may be K/(mn) respectively.