The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 1988
Filed:
Jun. 28, 1985
Richard D Pribnow, Chippewa Falls, WI (US);
Cray Research, Inc., Minneapolis, MN (US);
Abstract
An interprocessor communication system for a multiprocessor data processing system includes a common control circuit which includes a plurality of clusters where each cluster includes a plurality of semaphore registers and a plurality of information registers. Each type of register may be directly addressed by any processor. Each processor has a cluster code indicative of which, if any, of the clusters the processor may access. Each processor has a local control circuit in relatively close physical proximity and each local control circuit can communicate with the other local control circuits to determine whether one of its counterparts is requesting an operation. The local control circuit monitors and controls the issuance of the processor's instructions to the common control circuit. The local control circuit includes a plurality of local semaphore registers maintained with a copy of data in the common semaphore register cluster associated with that processor. The local control circuit further includes means for testing the status of a bit in the local semaphore register in response to a processor instruction requesting that the corresponding bit in the common control circuit be test and set, and for providing for the immediate issue of the instruction in the case where the bit is clear and the instruction may issue. The local control circuit also has the capability of generating a deadlock interrupt to accomodate the execution of a multiprocessing task by a single processor and to eliminate the possibility of a processor holding issue on a test and set instruction indefinitely.