Semiconductor memory device having stacked-capacitor type memory cells

Abstract

A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer. The semiconductor memory device further includes an additional conductive layer directly connected to the other of the source and drain regions of the transfer transistor in the memory cell, through the first insulating layer covering same, and extending over the gate of the adjoining transfer transistors. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. A method for manufacturing a semiconductor memory device having the above construction.