Method and apparatus for qualifying the decode window margin of a phase

Abstract

An ultra-compact window margin performance test apparatus for PLL data synchronizer integrated circuits includes self-contained programmable digital pattern generator, a moveable test bit generator capable of continuously adjustable bit delay time and bit pulse width for up to 25 megabit per second data rate operation. The apparatus also includes two independent oscillators for the 2F reference clock and for general system timing, a selectable Early/Late strobe or window center adjustment, and monitoring signals directly output to oscilloscope and ratio counter for accurate measurement of window margin data. The apparatus may be used to evaluate the bit tolerance merit of the PLL DUT. It may also be used as a design tool for basic PLL analysis and loop filter design optimization works. Additionally, the apparatus is a standardized correlation fixture suitable for use in quality assurance and manufacturing environments. Additionally, a method of static window and phase margins check for a decoding bit under test is employed to characterize the available window width of the PLL DUT and a convenient means as incorporated to optimize these margins.