The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 1988

Filed:

Oct. 21, 1986
Applicant:
Inventors:

John S Lechaton, Wappingers Falls, NY (US);

Philip M Pitner, Palo Alto, CA (US);

Gurumakonda R Srinivasan, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 34 ; 357 89 ; 357 90 ; 357 50 ;
Abstract

There is described a process for making a high performance NPN bipolar transistor functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body wherein the transistor includes an N+ subcollector, an N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through region, an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region located extending from the major surface and adjacent to the emitter region. The extrinsic base preferrably completely surrounds or rings the emitter region. A mask is formed above the major surface and the mask has openings therein only in the areas above major portions of the extrinsic base regions. A P+ type region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made to the elements of the transistor and the elements are connected in a current switch logic circuit. The use of the high conductivity P+ region in the extrinsic base region closely adjacent to the emitter substantially reduces the extrinsic base resistance. Since the extrinsic base region resistance is reduced, it is possible to reduce the size of the emitter area. Independent doping in the extrinsic base through the mask openings also allows independent control of the intrinsic and extrinsic base resistances. The result of these changes substantially increase the performance of bipolar transistor integrated circuits for current switch logic applications.


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