The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 1988

Filed:

Aug. 20, 1986
Applicant:
Inventors:

Arthur C Adams, Berkeley Heights, NJ (US);

Loren N Pfeiffer, Harding Township, Morris County, NJ (US);

Kenneth W West, Mendham, NJ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; C30B / ;
U.S. Cl.
CPC ...
437 84 ; 156603 ; 437 21 ; 437 29 ; 437942 ;
Abstract

Disclosed are methods that result in substantial improvement of silicon-on-insulator (SOI) device manufacture. We have discovered that carbon can be advantageously used as a wetting agent in the melting-recrystallization (MR) method of producing SOI wafers. We have also found that contacting the wafer (typically subsequent to the formation thereon of a poly-Si layer on a SiO.sub.2 layer but prior to the completion of formation of a SiO.sub.2 cap layer on the poly-Si layer) with an atmosphere that comprises a wetting agent-containing molecular species (e.g., CH.sub.4, NH.sub.3), with the wafer at an appropriate elevated (e.g., 500.degree.-900.degree. C.) temperature, can reliably result in recrystallized Si films of high quality. Furthermore, we have discovered the existence of a previously unknown parameter regime (low thermal gradient across the resolidification front, typically no more than about 4.degree. C./mm) for the MR process that can result in a highly perfect (.chi.min of 3%, subboundary spacing of about 50 .mu.m, misalignment across subboundaries of the order of 0.1.degree.) resolidified Si layer. Devices can be fabricated directly in this layer, or the layer can be used as seed substrate for the growth of a 'thick' epitaxial Si layer of the type useful for the fabrication of high voltage semiconductor devices.


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