Process for the production of bipolar transistors and complementary mos

Abstract

A process for the simultaneous production of bipolar transistors and CMOS transistors on a substrate using very large circuit integration (VLSI) semiconductor technology, modified by additional process steps in such a way that a decoupling of the two types of transistors is obtained with respect to the process. This is achieved by the use of a protective oxide above the active zones of the CMOS transistors during the production of the bipolar-specific base zones and by employing a gate electrode material in two layers, the second layer being used for the emitter and collector zone, resulting in a decoupling of phosphorus doping used for forming MOS gates, and arsenic doping used for polysilicon emitters. The use of the same resist mask for the gate structuring and the production of the emitter contact, and also for the production of the source/drain terminal zones, serves to keep the implanted phosphorus out of the emitter zone. The process is used to produce VLSI circuits containing high speed CMOS and bipolar transistors.