Bit line equalization in a memory

Abstract

A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.