The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 1988

Filed:

Jul. 10, 1985
Applicant:
Inventors:

Masao Kawachi, Mito, JP;

Yasufumi Yamada, Mito, JP;

Mitsuho Yasu, Katsuta, JP;

Hiroshi Terui, Mito, JP;

Morio Kobayashi, Mito, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B / ; G02B / ;
U.S. Cl.
CPC ...
350 9611 ; 350 9610 ; 350 9612 ; 350320 ;
Abstract

A hybrid optical integrated circuit having a high-silica glass optical waveguide formed on a silicon substrate, an optical fiber and an optical device coupled optically to the optical waveguide, and an optical fiber guide and an optical device guide on the substrate for aligning the optical fiber and the optical device at predetermining positions, respectively, relative to the optical waveguide. Islands carrying electrical conductors are disposed on the substrate. A first electrical conductor film is formed on the substrate. Second electrical conductor films are formed on the top surfaces of the optical waveguide, the optical fiber guide, the optical device guide and the islands and are electrically isolated from the first electrical conductor film. An electrical conductor member is provided to feed electric power from the first and second electric conductor films to the optical device which needs the power supply. The optical waveguide, the optical fiber guide, the optical device guide and the islands are formed from the same high-silica glass optical waveguide film. Alignment of various portions is facilitated when assembling the circuit. A high coupling efficiency is realized with a low cost.


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