The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 1988

Filed:

Jun. 24, 1987
Applicant:
Inventor:

Yoshihisa Okita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437228 ; 437238 ; 20419237 ;
Abstract

In a process of fabricating a semiconductor IC having a plurality of metal wiring conductor layers on a semiconductor substrate and an insulation layer between the metal wiring conductor layers, the insulation layer being formed of a silicon oxide film is formed by means of RF bias-sputtering, a silicon oxide film is formed by means of RF bias sputtering under such a condition that the deposition rate and the etching rate on a pattern surface 45.degree. inclined with respect to the reference surface of the semiconductor substrate are equal, part of the silicon oxide film over the underlying metal wiring conductor layer being protruded; a trench is formed in part of the silicon oxide film covering the metal wiring conductor layer, and the silicon oxide is etched by RF bias sputtering under such a condition that the deposition rate and etching rate on a pattern surface parallel to the reference surface of the semiconductor substrate are equal, until the protrusion of the silicon oxide film over the metal wiring conductor is removed so that the entire silicon oxide film is planarized.


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