The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 1988

Filed:

May. 05, 1987
Applicant:
Inventors:

Takao Umeda, Mito, JP;

Tetsuya Nagata, Hitachi, JP;

Yuzuru Simazaki, Hitachi, JP;

Tatsuo Igawa, Kitaibaraki, JP;

Yasuro Hori, Katsuta, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F / ; G09G / ;
U.S. Cl.
CPC ...
350332 ; 3503 / ; 350333 ; 340805 ;
Abstract

A multiplexed driving method of an optical switching element employing ferroelectric liquid crystal with a negative dielectric anisotropy including signal electrodes and common signal electrodes arranged in matrix and a ferroelectric liquid crystal layer disposed therebetween so as to constitute pixels at the respective facing portions of the signal electrodes and the common signal electrodes comprising a step of applying a common writing signal voltage to one of the common signal electrode to select pixels to which information be written, simultaneously applying a common status holding AC signal voltage to the other common signal electrodes covering non-selected pixels and simultaneously applying one of two signal pulses with opposite polarities to the signal electrodes, whereby resultant information writing voltages formed in combination of the common writing signal voltage and the signal pulses, which are enough to determine the orientation of the ferroelectric liquid crystal molecules, are applied on the selected pixels and resultant AC status holding voltage formed in combination of the common status holding AC signal voltage and the signal pulses which determine the limited bias voltage for the resultant AC voltage are applied on the non-selected pixels.


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