The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 1988
Filed:
Feb. 28, 1986
James Yu, San Jose, CA (US);
Hong-Gee Fang, San Jose, CA (US);
Moon-Yee Wang, San Jose, CA (US);
Robin W Cheung, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The substrate active region contains the source and drain regions for the transistors in each cell. The grounded drains of the two pulldown transistors extend symmetrically into the three adjacent cells coupling with six other pulldown drains. This common ground node has a single upward contact to the metal ground lead. The poly-2 has a similar voltage node coupling eight pulldown resistors in four adjacent cells to the metal Vdd lead. The poly-2 forming the lightly doped resistor area has a heavily doped conductive area at each end for coupling the resistor into the pulldown circuit. The pulldown gate bands have 45 degree bends to maximize the gate area relative to the pass gate area. The gate bends cooperate with corresponding 45 degree slants in the edges of the active region to minimize the effect of misalignment. A conductive poly word line forms the pass gates just above the active region. A metal word line connects periodically with the poly word line to minimize the effect of the distributive resistance of poly. Poly-2 is used to build up the contact from the drains of the pass transistor in the substrate active region to the metal bit leads. The lateral spread of the contact aperture is limited leaving a marging of insulating oxide between the bit contact and the pass gate structure.