Frequency response compensation circuit

Abstract

A frequency response compensation circuit includes a first forward gain stage and second reverse gain stage coupled to the first stage in negative feedback mode. The reverse gain stage depresses the gain of the first stage at low frequencies. When the frequency response of the reverse gain stage begins degrading, which corresponds to the frequency of the real zero of the compensation circuit, the gain of the compensation circuit begins increasing and increases until the gain of the reverse stage is zero. The circuit utilizes a pair of NPN transistors in the first stage, a pair of PNP transistors in the second stage and includes no capacitors or inductors. Thus, the circuit can be implemented as a semiconductor integrated circuit. By proper selection of the resistance values of the resistors in the circuit, the zero of the compensation circuit can be chosen to correspond generally to the frequency of the pole of the uncompensated input signal, so as to increase the bandwidth of the resultant signal. Multiple reverse gain stages can be included, with a selected reverse gain stage switched into connection with the first stage, so as to provide, generally, a constant frequency response for different input signals having different frequency responses.