Multiple port memory array device including improved timing and

Abstract

An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the second transition signals and for detecting a match in the first and second combinations of binary address signals and for providing a respective first status signal in an inactive state in response to the first transition signal and for providing a respective second status signal in an inactive state in response to the second transition signal.