Vital processing system adapted for the continuous verification of vital

Abstract

Continuous verification of vital (fail-safe) outputs from an information processing system is obtained without the need for large computing capacity (overhead). Multibit test sequences are provided continuously during successive subparts of the processor system cycle to vital output interfaces which invert the bits of the signals or do not pass them depending upon the state of the output. A compiler including a random access memory (RAM) addressed by a read only memory (ROM) is configured to divide each sequence by direct and inverse polynomials on alternately occurring parts of the system cycle to provide compressed data. After each part of the system cycle, checkwords are constructed using the resultant compressed data corresponding to each output which must be proven to be in its `off` state. These checkwords are used to verify the vital operation of the system and may be applied to a vital decoder which controls the application of operating power to the output interfaces to disconnect operating power therefrom and condition the outputs to the restrictive state upon detection of a failure which may occur at any time during the entire system cycle.